1. Field of the Invention
The present invention relates to a semiconductor device used for electric-power control utilizing a direct-lead-bonding method and, in particular, to a semiconductor-chip surface configuration.
2. Description of the Related Art
Currently, for power semiconductor devices used for electric power applications, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors), there has been a need for reduction of device resistances, in order to reduce the losses when applying current. As a method for realizing the aforementioned need, there has recently been employed a direct-lead-bonding method which directly connects leads to the semiconductor chip surface, instead of bonding methods using aluminum-wire bonding.
In general, semiconductor chips include electrodes made of an aluminum alloy. Accordingly, leads can not be directly connected to surfaces of the electrodes through soldering, and therefore a metal film containing nickel or the like which is connectable to solder is formed, in advance, on the aluminum alloy electrodes of the chips, through a vapor deposition method.
After the vapor-deposition of the metal film and before the soldering of the lead terminals, the chips are subjected to a process for performing screening tests by bringing probe needles into contact with the chip surface. This process is referred to as a probe test or a wafer test (hereinafter, referred to as the probe test). Typically, electric-power semiconductor devices are supplied with large electric currents during utilization. Therefore, during the probe test, a plurality of needles are brought into contact with the electrodes at the surfaces in order to flow a large electric current therethrough. Since surface electrodes are made of an aluminum alloy and are soft, then, deep probe-needle trances are left on the electrode aluminum alloy. In the case of semiconductor devices utilizing wire-bonding methods rather than the direct-lead-bonding method, even if needle trances are left, the damages at needle traces will not induce electric-field concentrations and stress concentrations during actual utilization after the assembly of the package and thus will induce no problem. However, in the case of utilizing the direct-lead-bonding method, leads are bonded through soldering, which causes intrusion of solder into needle trances. Conventionally, lead terminals have been bonded while allowing such intrusion of solder.
FIG. 38 is a plan view of a semiconductor device 50 suitable for the direct-lead-bonding method which is fabricated according to a conventional example. FIG. 39 is a plan view illustrating a semiconductor wafer 1 which has been subjected to processing steps until the final processing step, prior to the vapor deposition of the metal film. FIG. 40 is a plan view illustrating the back surface thereof. FIG. 41 is a plan view of a metal mask 7 for vapor-depositing the metal film on the emitter electrode 3 on a front surface. FIG. 42 is a schematic view illustrating the structure before the vapor deposition. FIG. 43 is a plan view of the semiconductor wafer 1 after the vapor deposition of the metal film 8 on the emitter electrode 3 on the front surface. FIG. 44 is a schematic view illustrating the needle contacting state during the probe test for the wafer. FIG. 45 is a cross-sectional view of FIG. 44. FIG. 46 is a plan view of the conventional semiconductor device 50 after the probe test, illustrating probe traces 11 left on the emitter electrodes 3 through the metal film 8. FIG. 47 is a partial cross-sectional view of an electric-power semiconductor product fabricated using the conventional semiconductor device 50. FIG. 48 is a partially enlarged cross-sectional view of the probe trace a on the surface of the emitter electrode 3 of the electric-power semiconductor product of FIG. 47.
The semiconductor device 50 according to the conventional configuration can be provided as follows.
(a) First, a semiconductor wafer 1 is prepared. For convenience, in this case, IGBTs which function as gate driving devices are used. The semiconductor wafer 1 has been subjected to the final step of wafer processing steps and, thus, a plurality of semiconductor chips 2 have been arranged on the semiconductor wafer 1. Each of the chips 2 includes an emitter electrode 3 and a gate electrode 4 which are both made of an aluminum alloy. Also, gate wiring 5 is provided for surrounding the emitter electrode 3. A collector electrode 6 is formed on the back surface of the semiconductor wafer 1 by use of a vapor deposition method or a sputtering method. Further, on the emitter electrode 3, a metal film 8 is selectively formed, by use of a vapor deposition method, over soldering regions required for bonding lead terminals thereto. In the present exemplary conventional structure, an alloy of Ti/Ni/Au is vapor-deposited on the emitter electrode 3. The Ti is for enhancing the ohmic characteristic with respect to the emitter electrodes 203, the Ni is an adhesive for bonding to the solder and the Au is an oxidation protection agent for the Ni.
(b) Thereafter, a probe test is conducted for the semiconductor wafer 1 for determining whether each of the chips is a non-defective product or a defective product and for attaching ink marks on the chip surfaces of defective chips. In a commonly conducted probe test, a plurality of probe needles 9 are brought into contact with the emitter electrode 3 and a single probe needle 9 is brought into contact with the gate electrode 4 while the collector electrode 6 on the back surface is contacted with a wafer stage 10 by use of vacuuming. Hereinafter, there will be described an exemplary category of tests for N-channel type IGBTs, by exemplifying ON-voltage measurements. First, a controlling voltage (for example, a gate-emitter voltage of +15V) is applied to the gate electrode 4 and a plus bias is applied to the collector electrode 6 on the back surface while the emitter electrode 3 is maintained at ground to generate an electric current flowing between the emitter electrode 3 and the collector electrode 6. Under this condition, the collector-emitter voltage for generating a certain electric current is defined as an ON-voltage and, thus, specification tests are conducted. In general, electric-power semiconductor devices have basic performance for control of large electric currents and, when applying current, a large electric current must be flowed therethrough. However, there is a limit to the amount of electric current which can be flowed through a single probe needle. Accordingly, a plurality of probe needles are brought into contact with the emitter electrode 3. The collector electrode 6 on the back surface is turned on over the entire wafer surface through the stage, which ensures provision of a sufficient electric current thereto.
(c) After the probe test, dicing is performed to cut off the chips 2. At this time, many probe traces 11 are left on the emitter electrodes 3 and the metal film 8. While the probe test is performed for a wafer in general, probe test may be performed for separated chips after dicing, in view of the working efficiency.
As described above, the fabrication of the semiconductor device 50 according to an exemplary conventional structure is completed.
In order to complete the fabrication of the electric-power semiconductor product as the final product, as illustrated in FIG. 47, the collector electrode 6 on the back surface is mounted on a substrate 13 through solder 12. Next, a lead terminal 14 made of Cu or the like is connected, through solder 15, to the metal film 8 on the emitter electrode 3, in the conventional semiconductor device 50. While in the present exemplary conventional structure an aluminum wire 16 is bonded to the gate electrode 4, the gate electrode 4 may be connected in the direct-lead method, similarly to the emitter electrode. Thereafter, a molded resin 17 for sealing is applied thereto to complete the fabrication of the electric-power semiconductor product.
Also, there have been known techniques for forming openings in an insulation film at the upper surface of chips and soldering aluminum wiring and the like to the regions, as shown in Japanese Patent Laid-open Publication No. JP2003-218155.